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| overview the LC7442 and LC7442e are memory controller for pip (picture-in-picture) systems for tv sets and vcrs. since this ic includes 3 built-in d/a converter circuits on chip, a component-type pip system can be constructed by combining this product with memory and an a/d converter such as the lc7480. features horizontal resolution: 600 tv lines *1 three built-in d/a converter provided on-chip in the pip memory controller block high image quality display provided by vertical filter function frame display *2 built-in even/odd field determination circuit built-in pll circuit (requires external lpf) handles ntsc/pal, tv/vcr, and multi-mode systems (ntsc-pal) *3 sub-screen specifications display modes: 2-screen, 3-screen, and 4-screen *2 display on/off and frame on/off/color switching, wipe function supports switching between fixed (4 corners) and arbitrary (8-bit specification of vertical and horizontal position) display positions the size of the display area can be either variable or 1/9 of the main picture area, i.e 1/3 of the vertical and 1/3 of the horizontal dimensions of the screen horizontal resolution of about 250 dots (y signal) gradations (quantization): 64 (6 bits) operating power supply voltage: 5 v 10% package: qip64e, dip64s notes 1.when aspect correction is not performed d/a clock y 15.00 mhz r-y 3.75 mhz b-y 3.75 mhz 2. the specifications vary with the external memory as listed in the table below. display memory 256 k 1 m 1 screen d o 2 screens o 3 screens d 4 screens d single-screen display consists of displaying only one screen in 2-screen mode. o : both dynamic and static images can be frame displayed d : only dynamic images can be frame displayed : not possible 3. multi-mode is only supported when 1m of external memory is provided. 4. see the separate ?pplication note?document for details. cmos ic ordering number : en4412a 51795th (ot) / 73093jn no. 4412-1/22 LC7442, 7442e sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan pip controller
LC7442, 7442e package dimensions unit: mm unit: mm 3071-dip64s 3159-qfp64e pin assignments no. 4412- 2 /22 [LC7442] [LC7442e] sanyo: dip64s sanyo: qip64e block diagram LC7442, 7442e no. 4412- 3 /12 LC7442, 7442e no. 4412- 4 /21 component-t ype pip system structural diagram (using the LC7442 and lc7480) note: see the separate ?pplication note?document for details on applications. internal control registers all functions are operated by inputting control register settings as serial port data. bit msb lsb address 7 6 5 4 3 2 1 0 functions 01h sby stl n/p mul vdfs1 vdfs0 mod1 mod0 operating mode 02h fld-b fld-a mvs1 mvs0 kout-b kout-a fvp fhp display mode 03h vp7 vp6 vp5 vp4 vp3 vp2 vp1 vp0 display position (v) 04h hp7 hp6 hp5 hp4 hp3 hp2 hp1 hp0 display position (h) 05h wk-b wk-a wkvr-b wkvr-a ywk5 ywk4 ywk3 ywk2 frame color (y), control 06h pll6 pll5 pll4 pll3 rwk5 rwk4 rwk3 rwk2 pll, frame color (r-y) 07h vwipe hwipe dwipe wpmod bwk5 bwk4 bwk3 bwk2 wipe, frame color (b-y) 08h wvaj1 wvaj0 whaj1 whaj0 rvaj1 rvaj0 rhaj1 rhaj0 display adjustment 1 09h clpaj1 clpaj0 ycaj1 ycaj0 wkaj1 wkaj0 l l display adjustment 2 0ah pp bse-a bs5 bs4 bs3 bs2 bs1 bs0 display area note: l: enter data values of 0. operating modes mode [mod1] [mod0] number of sub-screens display description two-screen frame 0 0 2 (a, b) frame has screens a and b two-screen field 0 1 2 (a, b) field has screens a and b three-screen field 1 0 3 (b) field uses screen b for 3 screens as a single block four-screen field 1 1 4 (b) field uses screen b for 4 screens as a single block notes: field: the dynamic image is framed. a and b screen overlapped display is not allowed (including horizontal overlap). screens a and b screen a: the sub-screen displayed at the location of its 4 corners. (specified by fvp and fhp) screen b: sub-screen displayed at the location according to register data (specified by vp0 to vp7 and hp0 to hp7) function screen b screen a display on/off o o dynamic/static d d frame on/off o o frame color, fixed/data o o wipe * 5 o display area * 5 o d * 4 LC7442, 7442e no. 4412- 5 /12 o : can be controlled independently. d : can be controlled jointly. : not supported. notes: 4: controlled jointly with the b screen when bse-a = 1. 5: wipe and display area cannot be used at the same time. 6: an operation evaluation must be performed if the wipe function or the display area function is to be used. register data functions o : on, : off data address register h l notes 01h sby o standby mode (pll circuits stopped) stl o static screen (all writing stopped) n/p ntsc pal mode selection mul o multi-mode specification * vdfs1, vdfs0 vertical filter coefficient selection * mod1,mod0 operating mode specification 02h fld?, fld? field memory specification (in 2-screen field mode) mvs1, mvs0 dynamic image specification (write field selection) kout?, kout? o screen b/a display fvp, fhp four-corner fixed position specification 03h vp7 to vp0 screen b vertical position data 04h hp7 to hp0 screen b horizontal position data 05h wk?, wk? o d/a converter frame for screens b and a wkvr?, wkvr? register data fixed data d/a converter frame color selection for screens b and a ywk5 to ywk2 d/a converter frame color y data 06h pll6 to pll3 pll divisor specification (aspect correction function) * rwk5 to rwk2 d/a converter frame color r-y data 07h v, h, d, wipe o wipe type selection wpmod wipe display area wipe circuit function selection bwk5 to bwk2 d/a converter frame color b-y data 08h wvaj1, wvaj0 write vertical adjustment whaj1, whaj0 write horizontal adjustment rvaj1, rvaj0 display vertical adjustment rhaj1, rhaj0 display horizontal adjustment 09h clpaj1, clpaj0 a/d clamp position adjustment ycaj1, ycaj0 phase adjustment for c (r-y, b-y) with respect to y * wkaj1, wkaj0 d/a converter frame position adjustment * 0ah pp passing processing (normally set to h: see the application note) * bse-a o the a screen is linked to the b screen display area bs5 to bs0 display area (blanking) size specification LC7442, 7442e no. 4412- 6 /22 note: usage notes may apply for certain setting values. see the separate ?pplication note?document for details. function descriptions this section describes the functions supported when 1 mbyte of external memory is used. 2-screen frame mode *7, *9 2-screen field mode *8, *9 switching between a and a' and between b and b' can be performed independently. 3-screen field mode *8, *9 the 3 screens are handled as a single block, and the functions are the same as those for the b screen. 4-screen field mode *8, *9, *10 the 4 screens are handled as a single block, and the functions are the same as those for the b screen. notes: 7: frame display 8: frame display for dynamic images only (however, an overrun phenomenon occurs.) 9: two sub-screens cannot be displayed so that they share a scan line. examples: 10: the maximum vertical direction for the display area is 75%. display position of the b screen LC7442, 7442e no. 4412- 7 /22 vp: data in register vp0 to vp7 hp: data in register hp0 to hp7 LC7442, 7442e frame control wipe function note: the wipe function can only be used on the b screen. display area this function allows display in an intermediate state of the wipe operation. aspect correction horizontal direction compression or expansion is effected by changing the pll oscillator frequency. there are limitations on the values of this setting, so be sure to refer to the separate ?pplication note?document for details. vertical frame horizontal thickness memory map the 1 mbyte vram is divided into 4 fields. 0 col 511 (0, 0) (1, 0) (ars1, ars0) (0, 1) (1, 1) read selection mode ars1 ars0 screen state 2-screen frame automatic switching automatic switching by the field determination based on the position circuit of the a and b screens 2-screen field a screen = fld-a as above b screen = fld-b 3-, 4-screen field b0 * 0 0 (automatic switching) b1 * 0 1 b2 * 1 0 b3 * 1 1 * the order b0 to b3 is fixed. w rite selection dynamic image display is controlled by setting mvs0 and mvs1. mode ars1 ars0 2-screen frame automatic switching by the field [mvs0] determination circuit 2-, 3-, 4-screen field [mvs1] [mvs0] LC7442, 7442e no. 4412- 10 /22 wkaj: 4 steps in 132 ns increments d/a converter output 0 row 511 note: when [ycaj1,0] = 00, use care when setting [wkaj1,0] to values other than 00, since incorrect color data may appear at th e right edge. limitations when a 256 kbit m emory is u sed 1-screen display the following control registers have fixed values. dynamic image display the following control registers are taken as the display setting. [kout-b] [kout-a] [mvs1] [mvs0] description l l no sub-screen l h l l screen a is displayed h l l h screen b is displayed h h illegal combination control register table control register table for 256 kbyte systems. bit msb lsb address 7 6 5 4 3 2 1 0 description 01h sby stl n/p l vdfs1 vdfs0 l h active mode 02h l l l mvs0 kout-b kout-a fvp fhp display mode see item ?ynamic image display?above. registers starting at address 03h function the same as when 1 mbit of memory is used. multi-mode systems the multi-mode function cannot be used with 256 kbit vram since v-dancing occurs in dynamic images. notes on multi-mode (ntsc-p al) external memory multi-mode can only be used when 1m of external memory is provided. operating mode since vertical dancing occurs in moving images in modes other than two-screen frame mode, this can only be used with static images. when the main screen is ntsc and the subscreen is pal, images will be expanded vertically. as a result, images may go offscreen in the 3 and 4 screen field modes. vertical compression ratio since the number of scan lines in ntsc and pal differ, the ratios differ by 1/3 in accordance with the ratio of the number of scan lines. LC7442, 7442e no. 4412- 11 /22 [mod1] = l [mod0] = h [fld-b] = l [fld-a] = l kout-b and kout-a cannot be high at the same time (only 1 screen can be displayed) 2-screen filed mode LC7442, 7442e pin functions pin no. qip dip signal i/o connection function circuit type 40 48 ov i main screen vertical sync signal (negative polarity) 39 47 oh i la7403 or a sync main screen horizontal sync signal (negative polarity) 38 46 kv i separator ic sub-screen vertical sync signal (negative polarity) 37 45 kh i sub-screen horizontal sync signal (negative polarity) 47 55 sck i serial clock 46 54 sd i microprocessor serial data serial control 45 53 sde i enable 48 56 res i initialization circuit reset 44 52 test i v ss test (connect to v ss in normal operation) 2 10 wdo3 o memory 3 11 wdo2 o memory memory write data output 4 12 wdo1 o memory 5 13 wdo0 o memory 6 14 a8 o memory msb 7 15 a7 o memory 8 16 a6 o memory 9 17 a5 o memory address 10 18 a4 o memory (a8 is left open when a 11 19 a3 o memory 256 kbyte memory is used) 12 20 a2 o memory 13 21 a1 o memory 14 22 a0 o memory lsb 15 23 dt o memory 16 24 we o memory 17 25 ras o memory control signals 18 26 cas o memory 19 27 sc o memory 20 28 sodi3 i memory 21 29 sodi2 i memory memory read data 22 30 sodi1 i memory 23 31 sodi0 i memory continued on next page. no. 4412- 12 /22 continued from preceding page. pin no. qip dip signal i/o connection function circuit type 26 34 ad5 i lc7480 msb 27 35 ad4 i lc7480 28 36 ad3 i lc7480 input of a-to-d converted 29 37 ad2 i lc7480 digital data 30 38 ad1 i lc7480 31 39 ad0 i lc7480 lsb 32 40 ysw o lc7480 y signal selection 33 41 rsw o lc7480 r-y signal selection mpx switching signals 34 42 bsw o lc7480 b-y signal selection 35 43 adclk o lc7480 sampling clock 36 44 adclp o lc7480 clamp pulse 41 49 waku o la7403 frame pulse output 42 50 kout o la7403 main/sub switching signal (blanking) 43 51 kout2 o control signal 24 32 dv dd digital power supply 25 33 dv ss (for logic circuits and the line memory) 58 2 yaout o la7403 y signal 57 1 raout o la7403 r-y signal d/a output 56 64 baout o la7403 b-y signal 55 63 vref i lc7480 d/a connection 54 62 bias capacitor 59 3 av dd d/a analog power supply 60 4 av ss 63 7 ocp o lpf charge pump output 64 8 ofc i lpf oscillator control voltage input 61 5 or resistor oscillator range resistor main screen synchronization 62 6 ov dd power supply vco 1 9 ov ss 51 59 kcp o lpf charge pump output 50 58 kfc i lpf oscillator control voltage input 53 61 kr resistor oscillator range resistor sub-screen synchronization 52 60 kv dd power supply vco 49 57 kv ss LC7442, 7442e no. 4412- 13 /22 LC7442, 7442e specifications absolute maximum ratings at t a = 25 2 c, v ss = 0 v paramater symbol ratings unit maximum supply voltage v dd max ?.3 to +7.0 v maximum input voltage v in max ?.3 to v dd + 0.3 v maximum output voltage v out max ?.3 to v dd + 0.3 v allowable power dissipation pd 1 max (dip version) 500 mw pd 2 max (qfp version) 350 mw operating temperature t opr ?0 to +70 c storage temperature tstg ?5 to +125 c allowable o perating r anges at t a = ?0 to +70 c, v ss = 0 v ratings paramater symbol conditions min typ max unit power supply voltage v dd 4.5 5.0 5.5 v input high level voltage v ih1 cmos levels 0.7 v dd v v ih2 ttl levels 2.2 v input low level voltage v il1 cmos levels 0.3 v dd v v il2 ttl levels 0.8 v reference voltage v ref v ref pin 3.4 0.8 v dd v dd v electrical characteristics at t a = 25 2 c, v dd = 5 v 10%, v ss = 0 v ratings paramater symbol conditions min typ max unit output high level voltage v oh1 i oh = ? ma; pins kcp and ocp v dd ?1 v v oh2 i oh = ? ma; pins other than kcp and ocp v dd ?1 v output low level voltage v ol1 i ol = 1 ma; pins kcp and ocp 1.0 v v ol2 i ol = 2 ma; pins other than kcp and ocp 0.4 v operating current dissipation i dd d res: h the dv ss pin 20 ma i dd a ov, kv: 60 hz the av ss pin 21 ma i dd o oh, kh: 15 khz the ov ss pin 2 ma i dd k a/d data: 1010 the kv ss pin 2 ma output unloaded static current dissipation i dd s res: l, 10 a input pin dc, output unloaded input leakage current i lk v i = v dd , v ss ? 1 a output leakage current i oz v i = v dd , v ss ; pins kcp and ocp ? 1 a d/a output resistance r da 150 w note: there are 4 power supply pin systems. the power supplies are dv dd , av dd , ov dd , and kv dd , and they must be identical. descriptions are for v dd . the grounds are dv ss , av ss , ov ss and kv ss , and they must be identical. descriptions are for v ss . switching characteristics at t a = 25 2 c, v dd = 5 v 10%, v ss = 0 v ratings paramater symbol min typ max unit vertical sync signals pulse width t vw 1 s rise time t vr 50 ns fall time t vf 50 ns horizontal sync signals pulse width t hw 1 s rise time t hr 50 ns fall time t hf 50 ns serial data interface serial clock pulse width t scw 200 ns rise time t scr 50 ns fall time t scf 50 ns data setup t dsu 100 ns data hold t dh 30 ns interval t sci 2 s control pulse width t cw 200 ns rise time t cr 50 ns fall time t cf 50 ns setup t csu 200 ns hold t ch 200 ns no. 4412- 14 /22 serial data synchonization signals LC7442, 7442e no. 4412- 15 /22 LC7442, 7442e sub-screen digital processing specifications parameter ntsc (f h = 15734 hz) pal (f h = 15625 hz) sampling order y, r - y, y, b - y, y, -, y -, ????? frequency f t (mhz) 640 f h 10.070 10.000 only y 320 f h f ty 5.035 5.000 only r-y 80 f h f tr 1.258 1.250 only b-y 80 f h f tb 1.258 1.250 number of quantization bits 6 bits d/a converter y signal 960 f h clock (mhz) f cy 15.105 15.000 r-y signal 240 f h f cr 3.776 3.750 b-y signal 240 f h f cb 3.776 3.750 write number of dots (horizontal) 384 only y 256 only r-y 64 only b-y 64 vertical h count 80 84 read display number of dots (horizontal) 370 only y 250 only r-y 60 only b-y 60 vertical h count 75 83 memory w rite r ange when the display fine adjustment register (wvaj1, 0, whaj1, 0) is 0000. LC7442, 7442e initial settings res pin: reset this pin must be held low when power is first applied. internal control registers the table below lists the states of the registers following a reset. register state sby h kout?, kout? l pll6 l pll5 l pll4 h pll3 h registers other than the above are not initialized by a reset. serial data interface serial input format the first 8 bits of data following sde going low specify an address, and the next 8 bits are register data for that address. the last 8 bits of data are transferred to the incremented address. the address can be re-specified after switching sde from low to high to low again ( ). since the pll clock is not used for serial data transfer, data transfers can be performed when sby is high. however, data cannot be transferred to registers that are initialized by a reset. since there is no way to confirm that the transferred data was latched correctly, we recommend refreshing this data periodically. no. 4412- 18 /22 power supply (dv dd , av dd , ov dd , kv dd ) res t d : at least a few microseconds. notes: h: v dd level l: v ss level these states are set even if sby = h. since all system operations are stopped at this time, the data held in external memory cannot be retained. even/odd field determination circuit since this determination is based on the phase dif ference between the falling edges of ov and oh, these must be input with the following timing. note: kv and kh are similar to the above. a = 0.02 to 0.40 h b = 0.60 to 0.98 h however, if the pll aspect correction function is used, these values will differ. see the separate ?pplication note?document for details. the horizontal synchronization signal equalizing pulse must be removed. synchronization signals the LC7442 oh and kh pin inputs are set assuming that oh (and kh) are delayed 1 s from the video signal horizontal synchronization signal. since noise on the synchronization signal input pins (kv, kh, ov and oh) results in image distortion, care must be used in wiring these signals. since the sub-screen will be distorted if the synchronization signals are unstable, we recommend turning off display in such cases. sub-screen output t iming notes: a: the frame data position shown here is for the timing when registers wkaj0 and 1 are 00. b: whether frame data is present or not is switched by the size of the kout pulse. LC7442, 7442e no. 4412- 19 /22 video signal oh or kh LC7442, 7442e clamp pulse a/d converter clamp since clamp pulses are output with the timing shown in the figure below, it is setup to fall within the pedestal range. on reset and during standby, the kh signal goes to a positive polarity, and is output as such. d/a converter clamp digital data in the a region: msb lsb y d/a: 0 0 0 0 0 0 r-y d/a: 1 0 0 0 0 0 b-y d/a: 1 0 0 0 0 0 clamping is applied by the main screen horizontal synchronization signal. external control output t iming relationship with the lc7480 a/d converter note: since this circuit operates at the high speeds shown in this figure, care is required to keep leads as short as possible in the wiring used in this circuit. no. 4412- 20 /22 a/d input notes: 1: the conditions t3 > 0 s and t4 > 0.5 s must be met. 2: the value of 4.8 s for t1 is the value when registers clpaj0 and 1 are 00. d/a output sampling data (lc7480 output) video memory relationships this value of t is for situations when aspect correction is not applied. data write note: since this circuit operates at the high speeds shown in this figure, care is required to keep leads as short as possible in the wiring used in this circuit. refresh a cas before ras refresh cycle is used. data transfer ? serial read note: since this function operates at the high speeds shown in the figure, care is required to keep the leads as short as possi ble in the circuit wiring. caution: contact your sanyo representative before determining the memory to be used. LC7442, 7442e no. 4412- 21 /22 LC7442, 7442e ps no. 4412- 22 /22 this catalog provides information as of february, 1997. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. p. 3 block diagram 1 a/d converter 2 loop filter 3 loop filter 4 micro- processor 5 input data timing control 6 a/d control 7 sub-screen pll 8 field determination 9 main screen pll 10 serial data controller 11 vertical filter (calculation and line memory) 12 write address 13 read address 14 output buffer 15 control register 16 write data control 17 selector 18 memory control 19 read data control 20,21,22 d/a converter d/a converter d/a converter 23 output control 24 dual port dram: 256 kbytes or 1 mbyte p. 4 component-type pip system structural diagram 1 a/d clamp 2 reset 3 main vertical synchronization 4 main horizontal synchronization 5 sub-screen vertical synchronization 6 sub-screen horizontal synchronization 7 micro- processor 8 dual port ram 9 main/sub switching (blanking) 10 frame p. 7 function descriptions (1) main screen (2) or: p. 8 frame control (6) 1 sub-screen sub-screen (7) 1 there are 4 wipe types. 2 an operating time of about 1.0 seconds. 3 v wipe 4 h wipe 5 vh wipe 6 d wipe 7 off off off off LC7442 no. 4412- 23 /12 |
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